1. Field of the Invention
The present invention relates to devices for interfacing data terminal equipment (DTE) to communications networks in general and more particularly to circuit arrangements which improve the speed and number of addresses which are processed at the DTE in order to determine whether or not a frame on the network reaches its destination.
2. Prior Art
The use of local area networks (LANs) for interconnecting DTEs, such as computers, word processors or the like, is well-known. The conventional LAN includes a transmission media interconnecting a plurality of DTEs. A network interface card, also known as an adapter, is mounted in each one of the DTEs and couples each one of the DTEs to the transmission media. The adapter performs the functions which are necessary for the DTEs, also called stations, to exchange messages.
The adapter package each message in a frame which is transmitted onto the transmission media. Each frame includes a destination address in which the identity of the recipient station is inserted. Among the many functions which the adapter performs is the Address Recognition Function (ARF). The adapter uses the ARF to determine if the frame reaches its destination. The simplest implementation of the ARF is as follows: the adapter is provided with circuitry which compares an incoming destination address with its own or assigned address. If the address matches, the frame is copied. If the addresses do not match, the frame is not copied. The ARF is usually implemented as part of a VLSI chip. Due to the large number of functions which are implemented on the chip, space (surface area) is at a premium. As a result, the allotted surface area makes it possible to implement circuitry for recognizing only a limited number (usually two) of relatively short (three bytes or less) addresses. In the alternative, appropriating more of the chip space for implementing the ARF results in less surface area on which needed functions can be implemented.
U.S. Pat. No. 4,866,421 discloses an adapter with circuitry for limited address recognition. The limited address recognition is done in the protocol handler of a VLSI chip. In addition, external circuities are used to provide extended address recognition. Even though the patent provides improvement in the right direction, it falls short of meeting the needs of present and future LAN requirements because it does not provide for multiple group address recognitions. In addition, it does not provide address recognition for extended addresses. In general, an extended address means an address having more than thirty-two (32) bits.